SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The following are the PLLs in the device in MAIN domain:
Overview of the device PLLs with the reference clock options in MAIN domain is shown on MAIN Domain PLLs Integration. For more specific information about PLLs see PLLs Device-Specific Information.

The external muxes of choosing the reference clocks are glitch-free muxes.
MAIN_PLL0_HSDIV3, MAIN_PLL2_HSDIV7, MAIN_PLL14_HSDIV1, MAIN_PLL15_HSDIV3 are reserved on the device.