SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the hardware configuration options
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C158h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| GHWPARAMS6_31_16 | |||||||
| R | |||||||
| 1C26h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| GHWPARAMS6_31_16 | |||||||
| R | |||||||
| 1C26h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BUSFLTRSSUPPORT | BCSUPPORT | OTG_SS_SUPPORT | ADPSUPPORT | HNPSUPPORT | SRPSUPPORT | GHWPARAMS6_9_8 | |
| R | R | R | R | R | R | R | |
| 1h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GHWPARAMS6_7 | GHWPARAMS6_6 | GHWPARAMS6_5_0 | |||||
| R | R | R | |||||
| 0h | 0h | 20h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | GHWPARAMS6_31_16 | R | 1C26h | DWC_USB3_RAM0_DEPTH Reset Source: rst_mod_g_rst_n |
| 15 | BUSFLTRSSUPPORT | R | 1h | DWC_USB3_EN_BUS_FILTERS Reset Source: rst_mod_g_rst_n |
| 14 | BCSUPPORT | R | 0h | DWC_USB3_EN_BC Reset Source: rst_mod_g_rst_n |
| 13 | OTG_SS_SUPPORT | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 12 | ADPSUPPORT | R | 0h | DWC_USB3_EN_ADP Reset Source: rst_mod_g_rst_n |
| 11 | HNPSUPPORT | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 10 | SRPSUPPORT | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 9:8 | GHWPARAMS6_9_8 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 7 | GHWPARAMS6_7 | R | 0h | DWC_USB3_EN_FPGA Reset Source: rst_mod_g_rst_n |
| 6 | GHWPARAMS6_6 | R | 0h | DWC_USB3_EN_DBG_PORTS Reset Source: rst_mod_g_rst_n |
| 5:0 | GHWPARAMS6_5_0 | R | 20h | DWC_USB3_PSQ_FIFO_DEPTH Reset Source: rst_mod_g_rst_n |