Figure 12-47 shows the MLBSS block diagram. It includes the following functional blocks:
- MediaLB core – Implements the physical and link layer requirements of either a 3-pin or the 6-pin interface. Serial-to-parallel/parallel-to-serial are also implemented along with MediaLB frame synchronization.
- Routing fabric block – Manages the flow of data between the MediaLB core and the DMA block, implementing bus arbiter and muxing logic to the channel table RAM and the data buffer RAM.
- Channel table RAM (CTR) – Used for storing channel descriptors for managing accesses to dynamic buffers in the data buffer RAM.
- Data buffer RAM (DBR) – Provides dynamic circular buffering between the transmit and receive devices.
- Memory interface – Implements a bridge between the configuration TeraNet_CFG slave interface and the channel table RAM or data buffer RAM interfaces.
- DMA – Implements a bus bridge between the DMA master and the routing fabric block.
- Registers – Used for configuration.
- Interrupt logic.
- RAT – The MLBSS natively supports
32-bit addressing. As the SoC has 40-bit address bus a RAT module is put on the
MLBSS master interface to translate the 32-bit addresses into 40-bit system
addresses. For information about the RAT module functionality, see
Region-based Address Translation (RAT) Module.
- ECC Aggregator – Performs single
error correction and double error detection over the DBR. For information about
the ECC aggregator functionality, see ECC Aggregator.