SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
A total of 7 destination channels are provided within the DMA for concurrent transfers from Tx per channel buffers to the various attached peripherals. Each Tx channel requires a single PSI-L thread. The Tx channels are allocated as shown in Table 11-81.
| Tx DMA Channel | Function | Channel Type | Trigger Mode | Data FIFO Address | Strobe MMR Address | Control FIFO Address |
|---|---|---|---|---|---|---|
| 8000 | USART 0 Tx Ch 0 | XY | edge | 000002800000 | 000000000000 | 000000000000 |
| 8001 | USART 1 Tx Ch 0 | XY | edge | 000002810000 | 000000000000 | 000000000000 |
| 8002 | USART 2 Tx Ch 0 | XY | edge | 000002820000 | 000000000000 | 000000000000 |
| 8003 | USART 3 Tx Ch 0 | XY | edge | 000002830000 | 000000000000 | 000000000000 |
| 8004 | USART 4 Tx Ch 0 | XY | edge | 000002840000 | 000000000000 | 000000000000 |
| 8005 | USART 5 Tx Ch 0 | XY | edge | 000002850000 | 000000000000 | 000000000000 |
| 8006 | USART 6 Tx Ch 0 | XY | edge | 000002860000 | 000000000000 | 000000000000 |