The device utilize an integrated On-Chip Static Random Access Memory (OCSRAM). Controllers for external memory sources such as DDR are not included. The key functionality of the OCSRAM module includes:
- Total of up to 6 MB of RAM
- Can be used as code and data memory by the R5FSS cores
- Can be used as data buffers accessible by DMA
- Four 64-bit wide independent banks of size 512KB with 200Mhz operating frequency
- Accessible by all initiator modules via the CORE_VBUSM interconnect as detailed in
- Protected with MPU firewalls as detailed in MPU
- Loadable space for the Secondary Bootloader (SBL) as detailed in
- 64-bit ECC Support
- Read-Modify-Write mechanism to support ECC update on memory writes less then 64-bits. Read-Modify-Write operation works independently per bank and requires one additional cycle to update.