SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register returns the most significant 16-bits of the external global timestamp counter loaded from a shadow register. The shadow register is updated every time the Trace Time Stamp Counter Register 0 is read. The value read from this register may be stale (or undefined) if software does not first read the Trace Time Stamp Counter Register 0.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 2020h |
| C7X256V1_DEBUG | 0007 3800 2020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| GLOBAL_TIMESTAMP | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GLOBAL_TIMESTAMP | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | R/W | 0h | reserved |
| 15:0 | GLOBAL_TIMESTAMP | R/W | 0h | Bits 47:32 of the external global timestamp read from a shadow register which captures the most significant 16-bits of the global timestamp when the bottom 32-bits are read |