SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The tracking mechanism is capable of handling all input (baseband) and output (audio) sampling rates used by HD Radio. The ATL works on a single-clock domain and is insensitive to a particular choice of the master clock frequency as long as it is divisible by the desired audio frequency.
The ATL consists of two circuits: Measurement Circuit and Adjustment Circuit.
The main interface includes two registers:
The measurement circuit includes an 8-bit rolling counter, a 16-bit rolling counter, and the 16-bit sample count register. The 8-bit counter counts audio clock cycles. The 16-bit counter counts the number of baseband samples received by the modem. When the 8-bit counter rolls over, the content of the 16-bit counter is strobed into the sample count from four compare clear registers (ATL0_BBSR, ATL1_BBSR, ATL2_BBSR, and ATL3_BBSR). The HD Radio library uses this content to determine the relative frequency offset between the audio clock and baseband sampling clock.
The adjusting circuit produces a timing signal at the top of the audio clock tree, which is used by dividers that make the audio timing signals including DAC oversampling clock, bit clock, and word select. The output is occasionally adjusted by altering the divide count by one “tick” of the master clock. It includes a 20-bit accumulator circuit with a 9-bit PPM from four compare clear registers (ATL0_PPMR, ATL1_PPMR, ATL2_PPMR, and ATL3_PPMR) and an adjustable clock divider from four compare clear registers (ATL0_ATLCR, ATL1_ATLCR, ATL2_ATLCR, and ATL3_ATLCR). The content of the four compare clear registers (ATL0_PPMR, ATL1_PPMR, ATL2_PPMR, and ATL3_PPMR) is subtracted from the accumulator every master clock (ATL_PCLK) cycle. On underflow, the audio clock divider adds or subtracts one master clock (ATL_PCLK) period from the nominal periods of the audio clocks. The rate of adjustments in PPM (parts-per-220) is exactly the value written to PPM from four compare clear registers (ATL0_PPMR, ATL1_PPMR, ATL2_PPMR, and ATL3_PPMR). The MSB or PPM from four compare clear registers (ATL0_PPMR, ATL1_PPMR, ATL2_PPMR, and ATL3_PPMR) of the PPM register determines whether the audio clock period is shortened or lengthened.
Figure 12-44 shows the ATL top-level block diagram.
Figure 12-44 ATL Block Diagram