SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is a constant register showing some PSC settings for easy debug. This register is read only.
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| Instance Name | Physical Address |
|---|---|
| WKUP_PSC0 | 0400 0600h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PWRDOM | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AUTOONLY | RESETISO | NEXTLOCK | ASYNC | ICEPICK | PERMDIS | PLLHANDSHAKE | NUMSCRDISBALE |
| R | R | R | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUMSCRDISBALE | NUMCLKEN | NUMCLK | |||||
| R | R | R | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:21 | RESERVED | NONE | 0h | Reserved |
| 20:16 | PWRDOM | R | 0h | Indicates which power domain this module belongs to Reset Source: chip_rst.chip_1_rst_n |
| 15 | AUTOONLY | R | 0h | 0: This LPSC supports all modes, 1: This LPSC supports Enable, AutoSleep or AutoWake only Reset Source: chip_rst.chip_1_rst_n |
| 14 | RESETISO | R | 0h | 0: This LPSC does not support Reset Isolation, 1: This LPSC supports Reset Isolation Reset Source: chip_rst.chip_1_rst_n |
| 13 | NEXTLOCK | R | 0h | 0: MDCTL.NEXT field is writable, 1: MDCTL.NEXT field is locked Reset Source: chip_rst.chip_1_rst_n |
| 12 | ASYNC | R | 0h | Async Lpsc Reset Source: chip_rst.chip_1_rst_n |
| 11 | ICEPICK | R | 0h | IcePick support Reset Source: chip_rst.chip_1_rst_n |
| 10 | PERMDIS | R | 0h | Permanently disable Reset Source: chip_rst.chip_1_rst_n |
| 9 | PLLHANDSHAKE | R | 0h | RTL parameter PLL_HANDSHAKE Reset Source: chip_rst.chip_1_rst_n |
| 8:6 | NUMSCRDISBALE | R | 0h | Number of PWR_SCR_DISABLE interfaces required on LPSC Reset Source: chip_rst.chip_1_rst_n |
| 5:3 | NUMCLKEN | R | 0h | Number of PWR_CLK_EN interfaces required on LPSC Reset Source: chip_rst.chip_1_rst_n |
| 2:0 | NUMCLK | R | 0h | Number of PWR_CLKSTOP interfaces required on LPSC Reset Source: chip_rst.chip_1_rst_n |