SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The RL2 does not modify the length of any transaction that the RL2 processes send to the slow memory it is intending to cache. As described earlier the RL2 allocation is based on full 32 byte read burst within the range of the specified target area. Once cached, any size or wrapping burst request to the same line can occur and can read the cached data. In the event that a allocated cache line returns an error on the read from the cacheable target, the allocation will restore the LRU aging such that the next allocated WAY is invalidated due to the target response error.