SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The procedure in Table 12-35 configures the MCASP pins for MCASP functionality.
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Configure module different pins to have MCASP functionality. | MCASP_PFUNC[31-0] | 0x0 |
| Configure the MCASP pins direction: AFSX AHCLKX ACLKX Desired n-th MCASP data pin AXRn is configured as an ouput for transmission. | MCASP_PDIR[28] AFSR; MCASP_PDIR[27] AHCLKR; MCASP_PDIR[26] ACLKR; MCASP_PDIR[n] AXRn | 0x-(1) 0x-(1) 0x-(1) 0x1 |