SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The memory interface block allows a direct software access to the channel table RAM. Any write to the MLB_MADR register triggers a single read or write cycle. Reading from the MLB_MADR register does not initiate a read or write access.
Table 12-76 shows a direct write to the channel table RAM.
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| Load the 128-bit data entry | MLB_MDAT0, MLB_MDAT1, MLB_MDAT2 and MLB_MDAT3 registers | -h |
| Enable writing data | MLB_MDWE0, MLB_MDWE1, MLB_MDWE2 and MLB_MDWE3 registers | 1h |
| Write the 8-bit channel table RAM target address | MLB_MADR[7-0] ADDR_7_0 | -h |
| Initiate a write cycle | MLB_MADR[31] WNR | 1h |
| Determine when the transfer is complete | Poll the MLB_MCTL[0] XCMP | 1h |
Table 12-77 shows a direct read from the channel table RAM.
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| Write the 8-bit channel table RAM target address | MLB_MADR[7-0] ADDR_7_0 | -h |
| Initiate a read cycle | MLB_MADR[31] WNR | 0h |
| Determine when the transfer is complete | Poll the MLB_MCTL[0] XCMP | 1h |
| Read the 128-bit data entry | MLB_MDAT0, MLB_MDAT1, MLB_MDAT2 and MLB_MDAT3 registers | -h |