SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Trace Control Register
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 2008h |
| C7X256V1_DEBUG | 0007 3800 2008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TCO | CPTM | TRIG_CHN_ENABLE | DLOST_CLR | PLOST_CLR | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TLOST_CLR | CONT_ENABLE | CIDS | CEMU | DBGM_SD | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| STALL_EN | HPI_MASK | CDAT | AEG_ACTIVE | GLOBAL_TIME_EN | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GLOBAL_TIME_EN | STREAM_EN | BRANCH_RBROADCAST | TCOMP_DISABLE | ||||
| R/W | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | TCO | R/W | 0h | Last Stall Standing Timing Compression Scheme |
| 29:27 | CPTM | R/W | 0h | Event Profiling Trace Mode These bits identify the mode in which trace is operating When an event profiling mode is configured this is equivalent to an enable to allow the data trace stream to be used for collection of event trace only Event trace is only collected in following cases though: In PEP mode: PC trace stream is enabled and AET PC trigger is currently allowing PC sample capture When one or more of the conditions is not met from being met then any partially buffered event trace messages are exported In AEP mode: Timing and PC trace streams are enabled and AET PC and Timing triggers are currently allowing PC sample capture When one or more of the conditions is not met from being met then any partially buffered event trace messages are exported In EEP mode: Timing trace stream is enabled and AET Timing trigger is currently allowing Timing sample capture When one or more of the conditions is not met from being met then any partially buffered event trace messages are exported In LSS mode: Same as for AEP mode When an event mode is configured, AET triggers pertaining to storing the data value part of memory transactions shall be ignored |
| 26 | TRIG_CHN_ENABLE | R/W | 0h | Trigger Channel Enable Enable chaining of the two applicaiton control and status registers to support an atomic 64-bit write access |
| 25 | DLOST_CLR | R/W | 0h | Clear the Data Trace Loss Sticky Status Bit |
| 24 | PLOST_CLR | R/W | 0h | Clear the PC Trace Loss Sticky Status Bit |
| 23 | TLOST_CLR | R/W | 0h | Clear the Timing Trace Loss Sticky Status Bit |
| 22:19 | CONT_ENABLE | R/W | 0h | Context Enable These bits should be changed when the PC and Data trace streams are both disabled Changing these bits when PC and/or Data Trace stream is enabled shall be ignored |
| 18 | CIDS | R/W | 0h | Continue during Interrupt During Suspend Allows recordign of activity related ot the servicing of an HPI while the CPU execution has been suspended by any type of debug action This bit should be changed prior to PC, Data, and Timing treams being enabled Changes after this may be ignored by hardware |
| 17 | CEMU | R/W | 0h | Continue during Debug Activity Allows the recording of stalls due to debug activity while the CPU execution has been suspended by any type of debug action or when CIDS=0 and foreground code execution is active This bit should be changed prior to the timing stream being enabled Changes made while the timing stream is enabled may be ignored by the hardware |
| 16 | DBGM_SD | R/W | 0h | DBGM Stall Disable |
| 15 | STALL_EN | R/W | 0h | CPU Stall Enable Controls the action taken when additional data from the CPU will cause buffers to lose data as the trace internal FIFO is full If set, the CPU will be stalled unless the DBGM bit is set or the application is currently in a HPI |
| 14 | HPI_MASK | R/W | 0h | HPI Mask This bti allows stalling the CPU while processing a high priority interrupt if the FIFO is getting full and STALL_EN bit is set |
| 13 | CDAT | R/W | 0h | CDAT Allows the recording of activity in the data trace stream either due to debug memory accesses being generated or due to an event trace mode such as EEP mode generating trace activity that is required to be collected in the data trace stream while the CPU execution has been suspended by any type of debug action or when CIDS=0 and foreground code execution is active This bit should be changed prior to the data stream or event trace mode being enabled Changes made whilst data stream is enabled [or an event trace mode is enabled] may be ignored by the hardware |
| 12:11 | AEG_ACTIVE | R/W | 0h | AEG_ACTIVE This bit reflects the total number of AEG events that are active for trace |
| 10:7 | GLOBAL_TIME_EN | R/W | 0h | Global Timestamp Enable These enables allow insertion of the global timestamps into trace streams below These bits should be set or cleared before the corresponding stream enables have been set Changing the values after the corresponding stream is enabled shall be ignored |
| 6:2 | STREAM_EN | R/W | 0h | Trace Stream Enables When an enable bit transitions from 0->1 all FIFO's and scoreboards associated with that stream are reset When an enable bit transitions from 1-> the stream may not be immediately disabled if scoreboards or partial trace packets have to be flushed but the bit4 shall change state immediately |
| 1 | BRANCH_RBROADCAST | R/W | 0h | Branch Broadcast This bit can be set to enable branch broadcasting mode This bit should be set or cleared before the PC trace stream is enabled Any changes made after the PC trace stream is enabled shall be ignored When branch broadcasting is enabled, PC offset compression is disabled for address parameters of branch and exception command packets and sign extended compression is enabled |
| 0 | TCOMP_DISABLE | R/W | 0h | Timing Stream Compression Disable This bit can be set to disable the timing stream compression This bit shoudl only be set or cleared when the instruction advance timing stream is disabled Any attempts to change this bit while the timing stream is enabled shall result in writes to this bit being ignored |