SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls the power clock gating feature of modules and busses
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 8284h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | CLKGATE_CTRL1_RAM5_NOGATE | CLKGATE_CTRL1_RAM4_NOGATE | CLKGATE_CTRL1_RAM3_NOGATE | CLKGATE_CTRL1_RAM2_NOGATE | CLKGATE_CTRL1_RAM1_NOGATE | CLKGATE_CTRL1_RAM0_NOGATE | |
| NONE | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 1h | 1h | 1h | 1h | 1h | 1h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CLKGATE_CTRL1_C7X_1_NOGATE | CLKGATE_CTRL1_C7X_0_NOGATE | RESERVED | ||||
| NONE | R/W | R/W | NONE | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED | NONE | 0h | Reserved |
| 29 | CLKGATE_CTRL1_RAM5_NOGATE | R/W | 1h | MAIN SRAM bank 5 auto clockgate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 28 | CLKGATE_CTRL1_RAM4_NOGATE | R/W | 1h | MAIN SRAM bank 4 auto clockgate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 27 | CLKGATE_CTRL1_RAM3_NOGATE | R/W | 1h | MAIN SRAM bank 5 auto clockgate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 26 | CLKGATE_CTRL1_RAM2_NOGATE | R/W | 1h | MAIN SRAM bank 2 auto clockgate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 25 | CLKGATE_CTRL1_RAM1_NOGATE | R/W | 1h | MAIN SRAM bank 1 auto clockgate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 24 | CLKGATE_CTRL1_RAM0_NOGATE | R/W | 1h | MAIN SRAM bank 0 auto clockgate on idle disable Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 23:13 | RESERVED | NONE | 0h | Reserved |
| 12 | CLKGATE_CTRL1_C7X_1_NOGATE | R/W | 0h | C7x_1 auto clock gate on idle disable. Field values (others are reserved): 1'b0 - Auto clock gating enabled 1'b1 - Auto clock gating disabled Reset Source: mod_por_rst_n |
| 11 | CLKGATE_CTRL1_C7X_0_NOGATE | R/W | 0h | C7x_0 auto clock gate on idle disable. Reset Source: mod_por_rst_n |
| 10:0 | RESERVED | NONE | 0h | Reserved |