SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Trip Zone Flag Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 002Ch |
| EPWM1 | 2301 002Ch |
| EPWM2 | 2302 002Ch |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | OST | CBC | INT | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:3 | RESERVED1 | R | 0h | Reserved |
| 2 | OST | R | 0h | Latched Status Flag for A One-Shot Trip Event 0h No one-shot trip event has occurred
1h Indicates a trip event has occurred on a
pin selected as a one-shot trip source.
This bit is cleared by writing the
appropriate value to the EPWM_TZCLR
register. |
| 1 | CBC | R | 0h | Latched Status Flag for Cycle-By-Cycle Trip Event 0h No cycle-by-cycle trip event has occurred
1h Indicates a trip event has occurred on a
pin selected as a cycle-by-cycle trip
source. The EPWM_TZFLG[1] CBC bit will
remain set until it is manually cleared by
the user. If the cycle-by-cycle trip event
is still present when the CBC bit is
cleared, then CBC will be immediately set
again. The specified condition on the pins
is automatically cleared when the EPWM
time-base counter reaches zero
(EPWM_TBCNT[15-0] TBCNT = 0000h) |
| 0 | INT | R | 0h | Latched Trip Interrupt Status Flag 0h Indicates no interrupt has been generated
1h Indicates an EPWMxTZINT interrupt was
generated because of a trip condition. No
further EPWMxTZINT interrupts will be
generated until this flag is cleared. If
the interrupt flag is cleared when either
CBC or OST is set, then another interrupt
pulse will be generated. Clearing all flag
bits will prevent further interrupts. This
bit is cleared by writing the appropriate
value to the EPWM_TZCLR register. |