SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The QoS MMR is integrated as part of data plane interconnect to provide programmability of priority, orderID and QoS sideband signals for each initiator port in the data plane. Currently the QoS sideband signal is not used for any routing or schedule purpose. For most of the initiator ports, it has only one setting of the orderID and QoS field. For the initiator port supports with multiple channels, the transactions in each channel can be programmed to have different sets of priority, orderID and QoS. The orderID is a four-bit field value. All the transactions coming from the same initiator ports with the same orderID expect to receive the read data in order.
In the previous generation of the interconnect, how the traffic is split among parallel paths to the same end points was hard coded. The traffic from a certain initiator port was hard coded to choose one of the parallel paths. Due to the nature of hard coded, the system could not load balance based on the use case. The current generation of interconnect removes this limitation by splitting traffic using the OrderID value. Since the orderID value for the traffic from each initiator port is programmable, the user can load balance based on the use case scenario.
Each target port in each SCR has its own arbiter. The SoC interconnect arbitration is based on priority. For the ports with equal priority, the arbiter uses round robin to break the tie.