| AASRC0 |
RX0_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_RXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_RXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_RXSYNC0_SEL[4:0 |
| AASRC0 |
RX1_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_RXSYNC1_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_RXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_RXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_RXSYNC1_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_RXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_RXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_RXSYNC1_SEL[4:0 |
| AASRC0 |
RX2_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_RXSYNC2_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_RXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_RXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_RXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_RXSYNC2_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_RXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_RXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_RXSYNC2_SEL[4:0 |
| AASRC0 |
RX3_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_RXSYNC0_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_RXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_RXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_RXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_RXSYNC3_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_RXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_RXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_RXSYNC3_SEL[4:0 |
| AASRC0 |
TX0_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_TXSYNC0_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_TXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_TXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_TXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_TXSYNC0_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_TXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_TXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_TXSYNC0_SEL[4:0 |
| AASRC0 |
TX1_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_TXSYNC1_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_TXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_TXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_TXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_TXSYNC1_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_TXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_TXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_TXSYNC1_SEL[4:0 |
| AASRC0 |
TX2_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_TXSYNC2_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_TXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_TXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_TXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_TXSYNC2_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_TXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_TXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_TXSYNC2_SEL[4:0 |
| AASRC0 |
TX3_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC0_TXSYNC3_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC0_TXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC0_TXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC0_TXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC0_TXSYNC3_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC0_TXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC0_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC0_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC0_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC0_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC0_TXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC0_TXSYNC3_SEL[4:0 |
| AASRC1 |
RX0_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_RXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_RXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_RXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_RXSYNC0_SEL[4:0 |
| AASRC1 |
RX1_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_RXSYNC1_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_RXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_RXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_RXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_RXSYNC1_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_RXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_RXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_RXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_RXSYNC1_SEL[4:0 |
| AASRC1 |
RX2_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_RXSYNC2_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_RXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_RXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_RXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_RXSYNC2_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_RXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_RXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_RXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_RXSYNC2_SEL[4:0 |
| AASRC1 |
RX3_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_RXSYNC0_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_RXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_RXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_RXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_RXSYNC3_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_RXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_RXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_RXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_RXSYNC3_SEL[4:0 |
| AASRC1 |
TX0_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_TXSYNC0_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_TXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_TXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_TXSYNC0_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_TXSYNC0_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_TXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_TXSYNC0_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_TXSYNC0_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_TXSYNC0_SEL[4:0 |
| AASRC1 |
TX1_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_TXSYNC1_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_TXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_TXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_TXSYNC1_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_TXSYNC1_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_TXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_TXSYNC1_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_TXSYNC1_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_TXSYNC1_SEL[4:0 |
| AASRC1 |
TX2_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_TXSYNC2_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_TXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_TXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_TXSYNC2_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_TXSYNC2_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_TXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_TXSYNC2_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_TXSYNC2_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_TXSYNC2_SEL[4:0 |
| AASRC1 |
TX3_SYNC_CLK |
HFOSC0_CLKOUT |
ASRC1_TXSYNC3_SEL[4:0] |
|
| ADC0_CLKSEL[1:0] |
| HFOSC1_CLKOUT |
ASRC1_TXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL1_HSDIV4_CLKOUT |
ASRC1_TXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| EXT_REFCLK1 |
ASRC1_TXSYNC3_SEL[4:0] |
| ADC0_CLKSEL[1:0] |
| MAIN_PLL4_HSDIV3_CLKOUT |
ASRC1_TXSYNC3_SEL[4:0] |
| MAIN_SYSCLK0/2 |
ASRC1_TXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV5_CLKOUT |
ASRC1_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL0_HSDIV6_CLKOUT |
ASRC1_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL4_HSDIV1_CLKOUT |
ASRC1_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_SYSCLK0 |
ASRC1_TXSYNC3_SEL[4:0] |
| CPSW_CLKSEL[2:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/10 |
ASRC1_TXSYNC3_SEL[4:0] |
| MAIN_PLL2_HSDIV1_CLKOUT/2 |
ASRC1_TXSYNC3_SEL[4:0 |