SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources. An eoi_write signal will be generated and another interrupt will be triggered if interrupt sources remain. This register will be reset one cycle after it has been written to.
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| Instance Name | Physical Address |
|---|---|
| FSS1_FSAS_0 | 0FC9 0010h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EOI_VECTOR | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | EOI_VECTOR | R/W | 0h | Write with bit position of targeted interrupt. (E.g. Ext FSS ECC is bit 0). Upon write, level interrupt will clear and if un-serviced will issue another pulse interrupt Reset Source: vbus_mod_g_rst_n |