SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes a new interrupt request to be generated.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 00C0h |
| MCASP1 | 02B1 00C0h |
| MCASP2 | 02B2 00C0h |
| MCASP3 | 02B3 00C0h |
| MCASP4 | 02B4 00C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED107 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED107 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED107 | XERR | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| XDMAERR | XSTAFRM | XDATA | XLAST | XTDMSLOT | XCKFAIL | XSYNCERR | XUNDRN |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED107 | R | 0h | |
| 8 | XERR | R/W | 0h | XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred. 0 No errors have occurred. 1 An error has occurred. |
| 7 | XDMAERR | R/W1TC | 0h | Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more serializers through the data port in a given time slot than were programmed as transmitters. Causes a transmit interrupt [XINT], if this bit is set and XDMAERR in XINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 has no effect. 0 Transmit DMA error did not occur. 1 Transmit DMA error did occur. |
| 6 | XSTAFRM | R/W1TC | 0h | Transmit start of frame flag. Causes a transmit interrupt [XINT], if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 has no effect. 0 No new transmit frame sync (AFSX) is
detected.
1 A new transmit frame sync (AFSX) is
detected. |
| 5 | XDATA | R/W1TC | 0h | Transmit data ready flag. Causes a transmit interrupt [XINT], if this bit is set and XDATA in XINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 has no effect. 0 XBUF is written and is full.
1 Data is copied from XBUF to XRSR. XBUF is
empty and ready to be written. XDATA is
also set when the transmit serializers are
taken out of reset. When XDATA is set, it
always causes a DMA event (AXEVT). |
| 4 | XLAST | R/W1TC | 0h | Transmit last slot flag. XLAST is set along with XDATA, if the current slot is the last slot in a frame. Causes a transmit interrupt [XINT], if this bit is set and XLAST in XINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 has no effect. 0 Current slot is not the last slot in a
frame.
1 Current slot is the last slot in a frame.
XDATA is also set. |
| 3 | XTDMSLOT | R | 0h | Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd. 0 Current TDM time slot is odd. 1 Current TDM time slot is even. |
| 2 | XCKFAIL | R/W1TC | 0h | Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt [XINT], if this bit is set and XCKFAIL in XINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 has no effect. 0 Transmit clock failure did not occur. 1 Transmit clock failure did occur. |
| 1 | XSYNCERR | R/W1TC | 0h | Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync [AFSX] occurs before it is expected. Causes a transmit interrupt [XINT], if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 has no effect. 0 Unexpected transmit frame sync did not
occur.
1 Unexpected transmit frame sync did occur. |
| 0 | XUNDRN | R/W1TC | 0h | Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR, but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt [XINT], if this bit is set and XUNDRN in XINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 has no effect. 0 Transmitter underrun did not occur.
1 Transmitter underrun did occur. For details
on McASP action upon underrun conditions,
see Buffer Underrun Error - Transmitter. |