SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 0420h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31 | DR | RESERVED_29_28 | WOE | WDE | WCE | CAS | |
| R | R | R | R/W | R/W | R/W | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_23 | PLC | PRC | OCC | RESERVED_19 | PEC | CSC | LWS |
| R | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PIC | PORTSPEED | PP | PLS | ||||
| R/W | R | R/W | R/W | ||||
| 0h | 0h | 1h | 5h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PLS | PR | OCA | RESERVED_2 | PED | CCS | ||
| R/W | R/W1TS | R | R | R/W1TC | R | ||
| 5h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED_31 | R | 0h | Reserved For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will fail [Timeout] if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended. |
| 30 | DR | R | 0h | Reset Value For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 29:28 | RESERVED_29_28 | R | 0h | Reserved |
| 27 | WOE | R/W | 0h | WOE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 26 | WDE | R/W | 0h | WDE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 25 | WCE | R/W | 0h | WCE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 24 | CAS | R | 0h | Cold Attach Status For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 23 | RESERVED_23 | R | 0h | Reserved For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. |
| 22 | PLC | R/W1TC | 0h | PLC For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 21 | PRC | R/W1TC | 0h | PRC For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not recommended. Reset Source: rst_mod_g_rst_n |
| 20 | OCC | R/W1TC | 0h | OCC For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 19 | RESERVED_19 | R/W1TC | 0h | WRC For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. |
| 18 | PEC | R/W1TC | 0h | PEC For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 17 | CSC | R/W1TC | 0h | CSC For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 16 | LWS | R/W | 0h | LWS For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 15:14 | PIC | R/W | 0h | PIC For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 13:10 | PORTSPEED | R | 0h | PORTSPEED For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 9 | PP | R/W | 1h | PP For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 8:5 | PLS | R/W | 5h | PLS For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 4 | PR | R/W1TS | 0h | PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_20_REGS/PORTSC_20/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended. Reset Source: rst_mod_g_rst_n |
| 3 | OCA | R | 0h | OCA For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 2 | RESERVED_2 | R | 0h | Reserved |
| 1 | PED | R/W1TC | 0h | PED For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 0 | CCS | R | 0h | CCS For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |