SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Hardware Breakpoint Address Mask Register 0 This register designates the LS 32-bits of the address qualifier mask
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0120h |
| C7X256V1_DEBUG | 0007 3800 0120h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| AMASK0 | |||||||
| R/W | |||||||
| 7FFFFFFFh | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| AMASK0 | |||||||
| R/W | |||||||
| 7FFFFFFFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AMASK0 | |||||||
| R/W | |||||||
| 7FFFFFFFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AMASK0 | RESERVED | ||||||
| R/W | R/W | ||||||
| 7FFFFFFFh | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | AMASK0 | R/W | 7FFFFFFFh | Program Address Reference [63:32] This field is initialized with the most significant 32-bits of a 64-bit address corresponding to the execute packet in which this hardware breakpoint resource is detecting |
| 0 | RESERVED | R/W | 0h | reserved |