SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Dead-Band Generator Control Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 001Eh |
| EPWM1 | 2301 001Eh |
| EPWM2 | 2302 001Eh |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | IN_MODE | POLSEL | OUT_MODE | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:6 | RESERVED1 | R | 0h | Reserved |
| 5:4 | IN_MODE | R/W | 0h | Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms, the default is EPWMxA In is the source for both falling and rising-edge delays 0h EPWMxA In (from the action-qualifier) is
the source for both falling-edge and
rising-edge delay.
1h EPWMxB In (from the action-qualifier) is
the source for rising- edge delayed signal.
EPWMxA In (from the action-qualifier) is
the source for falling-edge delayed signal.
2h EPWMxA In (from the action-qualifier) is
the source for rising- edge delayed signal.
EPWMxB In (from the action-qualifier) is
the source for falling-edge delayed signal.
3h EPWMxB In (from the action-qualifier) is
the source for both rising-edge delay and
falling-edge delayed signal. |
| 3:2 | POLSEL | R/W | 0h | Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0 Other enhanced modes are also possible, but not regarded as typical usage modes 0h Active high (AH) mode. Neither EPWMxA nor
EPWMxB is inverted (default).
1h Active low complementary (ALC) mode. EPWMxA
is inverted.
2h Active high complementary (AHC). EPWMxB is
inverted.
3h Active low (AL) mode. Both EPWMxA and
EPWMxB are inverted. |
| 1:0 | OUT_MODE | R/W | 0h | Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay 0h Dead-band generation is bypassed for both
output signals. In this mode, both the
EPWMxA and EPWMxB output signals from the
action-qualifier are passed directly to the
PWM-chopper submodule. In this mode, the
POLSEL and IN_MODE bits have no effect.
1h Disable rising-edge delay. The EPWMxA
signal from the action- qualifier is passed
straight through to the EPWMxA input of the
PWM-chopper submodule. The falling-edge
delayed signal is seen on output EPWMxB.
The input signal for the delay is
determined by the EPWM_DBCTL[5-4] IN_MODE
bit field.
2h Disable falling-edge delay. The EPWMxB
signal from the action- qualifier is passed
straight through to the EPWMxB input of the
PWM-chopper submodule. The rising-edge
delayed signal is seen on output EPWMxA.
The input signal for the delay is
determined by the EPWM_DBCTL[5-4] IN_MODE
bit field.
3h Dead-band is fully enabled for both rising-
edge delay on output EPWMxA and falling-
edge delay on output EPWMxB. The input
signal for the delay is determined by the
EPWM_DBCTL[5-4] IN_MODE bit field. |