SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
A channel initialization must be performed in order to ensure proper operation. Table 12-61 shows the sequence.
| Step | Crossreference |
|---|---|
| Configuring the hardware | Table 12-62 |
| Programming the routing fabric block | Table 12-63 |
| Programming the DMA block | Table 12-67 |
| Synchronizing and unmuting the synchronous channel | Table 12-70 |
Configuring The Hardware
To configure the MediaLB interface, the steps shown in Table 12-62 should be followed.
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| Clear channel table RAM, to ensure that no stray interrupts are generated | - | 0h |
| Clear the interrupt status bits for logical channels 0 to 63 | MLB_ACSR0 and MLB_ACSR1 | FFFF FFFFh |
| Mask all interrupts for DMA channels (from 0 to 63) | MLB_ACMR0 and MLB_ACMR1 | 0000 0000h |
| Select 3-pin or 6-pin MediaLB operation | MLB_MLBC0[5] MLBPEN | 0h for 3-pin 1h for 6-pin |
| Select MediaLB clock speed | MLB_MLBC0[4-2] MLBCLK | -h |
| Enable the MediaLB | MLB_MLBC0[0] MLBEN | 1h |
| Activate (unmask) all channels | MLB_HCMR0 and MLB_HCMR1 | FFFF FFFFh |
| Enable the HBI block | MLB_HCTL[15] EN | 1h |
| Set the DMA channel mask bits according to all active DMA channels | MLB_HCMR0 and MLB_HCMR1 | -h |
| Select DMA Mode 1 to be used | MLB_ACTL[2] DMA_MODE | 1h |
| Select software to clear the interrupts | MLB_ACTL[0] SCE | 1h |
| Enable MLBSS interrupts, if required | MLB_MIEN | -h |
Programming The Routing Fabric Block
The channel allocation table and channel descriptor table reside in the channel table RAM and are programmed indirectly through the memory interface block. The steps to be followed are shown in Table 12-63.
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| 1. Initialize all bits of the channel allocation table | - | 0h |
| 2. Select a connection label | CL | N = 0h to 3Fh |
| 3. Program the channel descriptor table for channel N | Use the memory interface registers to do a write to the channel descriptor table. See Table 12-64. | Mask to be used: FFFF FFFFh |
| 4. Program the channel allocation table for inbound data buffer RAM access | Write to the data buffer RAM. See Table 12-65. | - |
| 5. Program the channel allocation table for outbound data buffer RAM access | Read from the data buffer RAM. See Table 12-66. | - |
| 6. Repeat steps 2-5 to initialize all logical channels | - | - |
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| 1. Set the 14-bit base address | BA | -h |
| 2. Set the 12-bit or 13-bit buffer depth | BD (set this according to the BA so that it doesn’t overflow the buffer) | BD = buffer depth in bytes - 1 |
| IF: Synchronous channels | ||
| Set the 12-bit or 13-bit buffer depth | BD | (BD + 1) = 4 × frames per sub-buffer (m) × bytes per frame (bpf) |
| ENDIF | ||
| IF: Isochronous channels | ||
| Set the 12-bit or 13-bit buffer depth | BD | (BD + 1) mod (BS + 1) = 0 |
| ENDIF | ||
| IF: Asynchronous channels | ||
| Set the 12-bit or 13-bit buffer depth | BD | (BD + 1) >= max packet length (1024 for a MOST Data Packet (MDP)) |
| ENDIF | ||
| IF: Control channels | ||
| Set the 12-bit or 13-bit buffer depth | BD | (BD + 1) >= max packet length (64) |
| ENDIF | ||
| 3. For isochronous channels, configure the block size | BS | BS = block size in bytes - 1 |
| 4. Write to all other bits of the channel descriptor table | 0h |
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| For Tx channels the DMA block does the inbound data buffer RAM access | A Tx channel is from MLBSS to external host | - |
| For Rx channels MediaLB does the inbound data buffer RAM access | An Rx channel is from external host to MLBSS | - |
| Set the channel direction | RNW | 0h |
| Set the channel type | CT[2-0] | 0h: synchronous 1h: control 2h: asynchronous 3h: isochronous |
| Set the connection label | CL[5-0] | CL[5-0] = N |
| IF: CT[2-0] = 0h (synchronous) | ||
| Set the mute bit. | MT (the mute bit is set to avoid any flow of the garbage data that will be there in the data buffer prior to any transfer) | 1h |
| ENDIF | ||
| Set the channel enable bit | CE | 1h |
| Clear all other bits of the channel allocation table | - | 0h |
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| For Tx channels MediaLB does the outbound data buffer RAM access | A Tx channel is from MLBSS to external host | - |
| For Rx channels the DMA block does the outbound data buffer RAM access | An Rx channel is from external host to MLBSS | - |
| Set the channel direction | RNW | 1h |
| Set the channel type | CT[2-0] | 0h: synchronous 1h: control 2h: asynchronous 3h: isochronous |
| Set the connection label | CL[5-0] | CL[5-0] = N |
| IF: CT[2-0] = 000 (synchronous), | ||
| Set the mute bit. | MT | 1h |
| ENDIF | ||
| Set the channel enable bit | CE | 1h |
| Clear all other bits of the channel allocation table | - | 0h |
Programming The DMA Block
The DMA descriptor table resides in the channel table RAM and is programmed through TeraNet_CFG slave interface using the registers of the memory interface block. The steps to be followed are shown in Table 12-67.
| Step (1) | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| 1. Initialize all bits of the DMA descriptor table | - | 0h |
| 2. Select a connection label | CL (Note that the CL number chosen in this step should be equal to the CL number chosen in step 2 of Table 12-63) | N = 0h to 3Fh |
| 3. Program the DMA block ping page for channel N (2) | See Table 12-68 | - |
| 4. Program the DMA block pong page for channel N | See Table 12-69 | - |
| 5. Select big or little endian | LE | -h |
| 6. Select the active page | PG (Program this bit only once in the beginning of the configuration. It shouldn’t be touched by the software after that. The hardware updates this bit as the transactions happen) | -h |
| 7. Set the channel enable bit for all active logical channels | CE | 1h |
| 8. Repeat steps 2-7 for all active logical channels | - | - |
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| Set the 32-bit base address | BA1 | -h |
| Set the 11-bit buffer depth | BD1 | BD1 = buffer depth in bytes - 1 |
| IF: Synchronous channels | ||
| Set the 11-bit buffer depth | BD1 | (BD1+ 1) = n × frames per sub-buffer (m) × bytes-per-frame (bpf) |
| ENDIF | ||
| IF: Isochronous channels | ||
| Set the 11-bit buffer depth | BD1 | (BD1 + 1) mod (BS + 1) = 0 |
| ENDIF | ||
| IF: Asynchronous and control Rx channels | ||
| Set the 11-bit buffer depth | BD1 | 5 <= (BD1 + 1) <= 4096 (1) |
| ENDIF | ||
| IF: Asynchronous and control Tx channels | ||
| Set the 11-bit buffer depth | BD1 | 5 <= (BD1 + 1) <= 4096 (1) |
| Set the packet start bit if the page contains the start of the packet | PS1 | 1h |
| ENDIF | ||
| Clear the page done bit | DNE1 | 0h |
| Clear the error bit | ERR1 | 0h |
| Set the page ready bit | RDY1 | 1h |
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| Set the 32-bit base address | BA2 | -h |
| Set the 11-bit buffer depth | BD2 | BD2 = buffer depth in bytes - 1 |
| IF: Synchronous channels | ||
| Set the 11-bit buffer depth | BD2 | (BD2+ 1) = n × frames per sub-buffer (m) × bytes-per-frame (bpf) |
| ENDIF | ||
| IF: Isochronous channels | ||
| Set the 11-bit buffer depth | BD2 | (BD2 + 1) mod (BS + 1) = 0 |
| ENDIF | ||
| IF: Asynchronous and control Rx channels | ||
| Set the 11-bit buffer depth | BD2 | 5 <= (BD2 + 1) <= 4096 (1) |
| ENDIF | ||
| IF: Asynchronous and control Tx channels | ||
| Set the 11-bit buffer depth | BD2 | 5 <= (BD2 + 1) <= 4096 (1) |
| Set the packet start bit if the page contains the start of the packet | PS2 | 1h |
| ENDIF | ||
| Clear the page done bit | DNE2 | 0h |
| Clear the error bit | ERR2 | 0h |
| Set the page ready | RDY2 | 1h |
Synchronizing And Unmuting The Synchronous Channel
The steps to be followed are shown in Table 12-70
| Step | Register/ Bit Field/ Programming Model/ Comments | Value |
|---|---|---|
| Check that MediaLB clock is running | MLB_MLBC1[7] CLKMERR | 0h |
| IF: The MediaLB clock is not toggling at the pads | MLB_MLBC1[7] CLKMERR | 1h |
| Clear the register bit | MLB_MLBC1[7] CLKMERR | |
| Wait one MLBSS_PCLK or MLBSS I/O clock cycle | ||
| Check that MediaLB clock is running | MLB_MLBC1[7] CLKMERR | 0h |
| ENDIF | ||
| Poll for MediaLB lock | MLB_MLBC0[7] MLBLK | 1h |
| Wait four frames | - | - |
| Unmute the synchronous channel/channels | MT | 0h |