SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Control Register contains general control bits for the ospi
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| Instance Name | Physical Address |
|---|---|
| FSS1_OSPI_0 | 0FCC 4004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PIPELINE_MODE_FLUSH | RESERVED | |||||
| NONE | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3 | PIPELINE_MODE_FLUSH | R/W | 0h | 1 - Flush Cadence Flash Controller FIFO by forcin gAHB SEL low. 0 - AHB Sel to Cadence Controller is 1 Reset Source: psrst_n |
| 2:0 | RESERVED | NONE | 0h | Reserved |