SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indirect Write Transfer Control Register
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| Instance Name | Physical Address |
|---|---|
| FSS1_OSPI_0 | 0FCC 0070h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| INDIR_WR_XFER_RESV2_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| INDIR_WR_XFER_RESV2_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| INDIR_WR_XFER_RESV2_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NUM_IND_OPS_DONE_FLD | IND_OPS_DONE_STATUS_FLD | WR_QUEUED_FLD | INDIR_WR_XFER_RESV1_FLD | WR_STATUS_FLD | CANCEL_FLD | START_FLD | |
| R | R/W1TC | R | R | R | W | W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | INDIR_WR_XFER_RESV2_FLD | R | 0h | Reserved |
| 7:6 | NUM_IND_OPS_DONE_FLD | R | 0h | This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field [bit 5]. It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it. |
| 5 | IND_OPS_DONE_STATUS_FLD | R/W1TC | 0h | Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it. |
| 4 | WR_QUEUED_FLD | R | 0h | Two indirect write operations have been queued |
| 3 | INDIR_WR_XFER_RESV1_FLD | R | 0h | Reserved |
| 2 | WR_STATUS_FLD | R | 0h | Indirect Write Status: Indirect write operation in progress [status] |
| 1 | CANCEL_FLD | W | 0h | Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations. |
| 0 | START_FLD | W | 0h | Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation. |