SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
HSDIV_CTRL0 register for pll15
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| Instance Name | Physical Address |
|---|---|
| PLL0 | 0068 F080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESET | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLKOUT_EN | RESERVED | SYNC_DIS | |||||
| R/W | NONE | R/W | |||||
| 1h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | HSDIV | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESET | R/W | 0h | SSM reset. When set to 1 the SSM modulator is in resetl Reset Source: sys_por_arst_rst_n |
| 30:16 | RESERVED | NONE | 0h | Reserved |
| 15 | CLKOUT_EN | R/W | 1h | CLKOUT1 enable 1'b0 - Synchronously disable CLKOUT1 1'b1 - Synchronously enable CLKOUT1 Reset Source: sys_por_arst_rst_n |
| 14:9 | RESERVED | NONE | 0h | Reserved |
| 8 | SYNC_DIS | R/W | 0h | Disable divider synchronization logic 0 - Changes to DIV value synchronized to prevent glitches 1 - Changes are asynchronous Reset Source: sys_por_arst_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6:0 | HSDIV | R/W | 0h | CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127 Reset Source: sys_por_arst_rst_n |