SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PLL15_FREQ_CTRL1 - PLL0 Frequency Control 1 Register
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| Instance Name | Physical Address |
|---|---|
| PLL0 | 0068 F034h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| FB_DIV_FRAC | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FB_DIV_FRAC | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FB_DIV_FRAC | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RESERVED | NONE | 0h | Reserved |
| 23:0 | FB_DIV_FRAC | R/W | 0h | PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395. The total feedback divide value is (fb_div_int + fb_div_frac / (2^24)) 24'h000000 - 0 24'h000001 - .000000059605 (1/(2^24)) 24'h000002 - .000000119209 (2/(2^24)) : 24'h800000 - .500000000000 : 24'hFFFFFF - .999999940395 (1677215/(2^24)) Reset Source: sys_por_arst_rst_n |