SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
pll MMR Configuration
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| Instance Name | Physical Address |
|---|---|
| PLL0 | 0068 F008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| HSDIV_PRSNT | |||||||
| R | |||||||
| Fh | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| HSDIV_PRSNT | |||||||
| R | |||||||
| Fh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SSM_TYPE | RESERVED | SSM_WVTBL | ||||
| NONE | R | NONE | R | ||||
| 0h | 1h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PLL_TYPE | ||||||
| NONE | R | ||||||
| 0h | 1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | HSDIV_PRSNT | R | Fh | High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15. By definition HSDIV[4:0] are connected the PLL FOUTVCO output clock and HSDIV[15:5] are connected to the PLL FOUTPOSTDIV output clock Reset Source: sys_por_arst_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:11 | SSM_TYPE | R | 1h | Spread spectrum module presence Field values (Others are reserved): 2'b00 - SSM is not present 2'b01 - SSM is present 2'b10 - Reserved 2'b11 - Reserved Reset Source: sys_por_arst_rst_n |
| 10:9 | RESERVED | NONE | 0h | Reserved |
| 8 | SSM_WVTBL | R | 0h | Spread spectrum wave table presence 1'b0 - SSM Wave table is not present 1'b1 - SSM Wave table is present Reset Source: sys_por_arst_rst_n |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | PLL_TYPE | R | 1h | Indicates PLL type Field values (Others are reserved): 2'b00 - Fractional PLL 2'b01 - FractionalF PLL 2'b10 - De-Skew PLL Reset Source: sys_por_arst_rst_n |