SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PLL14_CTRL - PLL14 Control
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| Instance Name | Physical Address |
|---|---|
| PLL0 | 0068 E020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| BYPASS_EN | RESERVED | ||||||
| R/W | NONE | ||||||
| 1h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | BYP_ON_LOCKLOSS | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PLL_EN | RESERVED | INTL_BYP_EN | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLK_4PH_EN | CLK_POSTDIV_EN | RESERVED | DSM_EN | DAC_EN | ||
| NONE | R/W | R/W | NONE | R/W | R/W | ||
| 0h | 0h | 1h | 0h | 0h | 1h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | BYPASS_EN | R/W | 1h | Bypass enable. This controls the glitch-free bypass mux. The bypass_en bit should be set prior tomaking any changes to the PLL settings. 1'b0 - Synchronously select PLL and associated HSDIV clock outputs 1'b1 - Synchronously select the reference clock for all PLL and HSDIV clock outputs Reset Source: sys_por_arst_rst_n |
| 30:17 | RESERVED | NONE | 0h | Reserved |
| 16 | BYP_ON_LOCKLOSS | R/W | 1h | Bypass on loss of PLL lock. This bit controls the PLL bypass mux to automatically switch the clock source to the reference clock when the PLL losses lock. 1'b0 - Do not automatically switch to ref clock source on PLL lock loss 1'b1 - Switch to ref clock source when PLL losses lock Reset Source: sys_por_arst_rst_n |
| 15 | PLL_EN | R/W | 0h | PLL enable 1'b0 - PLL is disabled 1'b1 - PLL is enabled Reset Source: sys_por_arst_rst_n |
| 14:9 | RESERVED | NONE | 0h | Reserved |
| 8 | INTL_BYP_EN | R/W | 0h | PLL internal bypass enable. This is an asynchronous mux which can produce glitches on the outputclocks during switching. 1'b0 - Output clocks are derived from the VCO clock 1'b1 - Output clocks are derived from the FREF reference clock Reset Source: sys_por_arst_rst_n |
| 7:6 | RESERVED | NONE | 0h | Reserved |
| 5 | CLK_4PH_EN | R/W | 0h | Enable 4-phase clock generator. This bit is ignored if clk_postdiv_en=0 1'b0 - 4-phase dividers disabled. FOUT1PHx and FOUTn clocks are held low. 1'b1 - 4-phase dividers enabled. FOUT1PH0/90/180/270 and FOUT2, FOUT3, FOUT4 clocks are enabled. Reset Source: sys_por_arst_rst_n |
| 4 | CLK_POSTDIV_EN | R/W | 1h | Post divide CLK enable 1'b0 - Post divide powered down. FOUTPOSTDIV and all auxiliary PLL clocks (4-ohase and synchronous divided clocks) are held low 1'b1 - Post divide enabled. FOUTPOSTDIV, 4-phase and synchronous clocks are enabled. Reset Source: sys_por_arst_rst_n |
| 3:2 | RESERVED | NONE | 0h | Reserved |
| 1 | DSM_EN | R/W | 0h | Delta-Sigma modulator enable 1'b0 - Delta-Sigma modulator is disabled (use integer divide mode) 1'b1 - Delta-Sigma modulator is enabled (use fractional divide mode) Reset Source: sys_por_arst_rst_n |
| 0 | DAC_EN | R/W | 1h | Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0) 1'b0 - Fractional NC DAC is disabled (for Test modes only) 1'b1 - Fractional NC DAC is enabled (ignored in integer divide mode) Reset Source: sys_por_arst_rst_n |