SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PLL_SS_SPREAD register for pll7
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| Instance Name | Physical Address |
|---|---|
| PLL0 | 0068 7044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | MOD_DIV | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SPREAD | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | MOD_DIV | R/W | 1h | Input clock divider. This divider sets the modulation frequency. Supports divide values of 1-15 Reset Source: sys_por_arst_rst_n |
| 15:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | SPREAD | R/W | 1h | Sets the spread modulation depth. The depth is spread*0.1% 5'b00000 - Reserved (don't use) 5'b00001 - 0.1% 5'b00010 - 0.2% : 5'b10000 - 1.6% : 5'b11111 - 3.1% Reset Source: sys_por_arst_rst_n |