SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PLL0_FREQ_CTRL0 - PLL7 Frequency Control 7 Register
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| Instance Name | Physical Address |
|---|---|
| PLL0 | 0068 7030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | FB_DIV_INT | ||||||
| NONE | R/W | ||||||
| 0h | 10h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FB_DIV_INT | |||||||
| R/W | |||||||
| 10h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | RESERVED | NONE | 0h | Reserved |
| 11:0 | FB_DIV_INT | R/W | 10h | PLL feedback divider (integer portion) In Integer mode values of 16 - 3200 (dec) are supported. In Fractional mode values of 20 to 320 are supported. 12'h010 - Divide by 16 12'h011 - Divide by 17 : 12'h140 - Divide by 320 : 12'hC80 - Divide by 3200 12'hC81 - 12'hFFF - Not supported Reset Source: sys_por_arst_rst_n |