SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
PLL4_DIV_CTRL - PLL4 Output Clock Divider Register
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| Instance Name | Physical Address |
|---|---|
| PLL0 | 0068 4038h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | POST_DIV2 | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | POST_DIV1 | ||||||
| NONE | R/W | ||||||
| 0h | 2h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | REF_DIV | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | POST_DIV2 | R/W | 1h | Secondary post divider. Supports values of 1-7 Reset Source: sys_por_arst_rst_n |
| 23:19 | RESERVED | NONE | 0h | Reserved |
| 18:16 | POST_DIV1 | R/W | 2h | Primary post divider. To ensure correct operation, post_div1 must always be programmed to a value equal to or greater that post_div2. Supports values of 1-7i Field values (Others are reserved): 3'b000 - Reserved (do not use) 3'b001 - Divide by 1 3'b010 - Divide by 2 3'b011 - Divide by 3 3'b100 - Divide by 4 3'b101 - Divide by 5 3'b110 - Divide by 6 3'b111 - Divide by 7 Reset Source: sys_por_arst_rst_n |
| 15:6 | RESERVED | NONE | 0h | Reserved |
| 5:0 | REF_DIV | R/W | 1h | Reference clock pre-divider. Supports values of 1-63 6'b000000 - Reserved /(do not use/) 6'b000001 - Divide by 1 6'b000010 - Divide by 2 : 6'b111111 - Divide by 63 Reset Source: sys_por_arst_rst_n |