SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The CTI Channel to Trigger 3 Enable Registers define which channels can generate a ctitrigout[3] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 30ACh |
| C7X256V0_DEBUG | 0007 3400 A0ACh |
| C7X256V0_DEBUG | 0007 3400 B0ACh |
| C7X256V1_DEBUG | 0007 3800 30ACh |
| C7X256V1_DEBUG | 0007 3800 A0ACh |
| C7X256V1_DEBUG | 0007 3800 B0ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TRIGOUTEN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | TRIGOUTEN | R/W | 0h | Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[3] output. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register, the channel input (ctichin) from the CTM is routed to the ctitrigout output. For example, enabling bit 0 enables ctichin[0] to cause a trigger event on the ctitrigout[3] output. When a 0 is written to any of the bits in this register, the channel input (ctichin) from the CTM is not routed to the ctitrigout output. Reading this register returns the programmed value. |