SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 302Ch |
| C7X256V0_DEBUG | 0007 3400 A02Ch |
| C7X256V0_DEBUG | 0007 3400 B02Ch |
| C7X256V1_DEBUG | 0007 3800 302Ch |
| C7X256V1_DEBUG | 0007 3800 A02Ch |
| C7X256V1_DEBUG | 0007 3800 B02Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TRIGINEN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | TRIGINEN | R/W | 0h | Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels. When a 1 is written to a bit in this register, it enables the ctitrigin signal to generate an event on the respective channel of the CTM. For example, TRIGINEN[0] set to 1 enables ctitrigin onto channel 0. Writing a 0 to any of the bits in this register disables the ctitrigin signal from generating an event on the respective channel of the CTM. Reading this register returns the programmed value. |