SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Device Interrupt Moderation Register (DEV_IMOD) This register controls the Interrupt Moderation feature that allows the device software to throttle the interrupt rate. Key Functions: - Interrupt Moderation is enabled only when the IMOD Interval is programmed to a non-zero value. - Interrupt is asserted whenever the IMOD (down) counter is 0, EVNT_HANDLER_BUSY is 0, and there are pending events (that is, event count is non-zero) - GEVNTCOUNT[EVNT_HANDLER_BUSY] is set by hardware when interrupt is asserted, and cleared by software when interrupt processing is completed. - The Interrupt line is de-asserted after the first write to the event count. - IMOD counter is loaded with IMOD interval whenever the Interrupt line is de-asserted.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 CA00h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DEVICE_IMODC | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DEVICE_IMODC | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DEVICE_IMODI | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DEVICE_IMODI | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | DEVICE_IMODC | R/W | 0h | Interrupt Moderation Down Counter Loaded with the DEVICE_IMODI value, whenever the hardware interrupt[n] line is de-asserted from the asserted state, counts down to 0, and stops. The interrupt[n] is signaled whenever this counter is 0, EVNT_HANDLER_BUSY is 0, and there are pending events [that is, event count is non-zero]. This counter may be directly written by software at any time to alter the interrupt rate. Reset Source: rst_mod_g_rst_n |
| 15:0 | DEVICE_IMODI | R/W | 0h | Moderation Interval [DEVICE_IMODI] This field holds the minimum inter-interrupt interval between events. The interval is specified in terms of 250ns increments. A value of 0 disables the interrupt throttling logic and interrupts are generated immediately if event count becomes non-zero. In scaledown simulation mode, 4 ram clocks are used to time 250ns. Reset Source: rst_mod_g_rst_n |