SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Device Status Register This register indicates the status of the device controller with respect to USB-related events. Note: When Hibernation is not enabled, RSS and SSS fields always return 0 when read.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C70Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_30 | DCNRD | SRE | RESERVED_27_26 | RSS | SSS | ||
| R | R | R/W1TC | R | R | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| COREIDLE | DEVCTRLHLT | USBLNKST | RXFIFOEMPTY | SOFFN | |||
| R | R | R | R | R | |||
| 0h | 1h | 4h | 1h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SOFFN | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOFFN | CONNECTSPD | ||||||
| R | R | ||||||
| 0h | 4h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED_31_30 | R | 0h | Reserved |
| 29 | DCNRD | R | 0h | Device Controller Not Ready The bit indicates that the controller is in the process of completing the state transitions after exiting from hibernation. To complete the state transitions, it takes 256 bus clock cycles from the time DCTL[31].Run/Stop is set. During hibernation, if the UTMI/ULPI PHY is in suspended state, then the 256-bus clock cycle delay starts after the PHY exited suspended state. Software must set DCTL[31].Run/Stop to '1' and wait for this bit to be de-asserted to zero before processing DSTS.USBLnkSt. This bit is valid only when DWC_USB3_EN_PWROPT is set to 2 and GCTL[1].GblHibernationEn =1. Reset Source: rst_mod_g_rst_n |
| 28 | SRE | R/W1TC | 0h | Save Restore Error. Currently not supported. Reset Source: rst_mod_g_rst_n |
| 27:26 | RESERVED_27_26 | R | 0h | Reserved |
| 25 | RSS | R | 0h | RSS Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller finishes the restore process, it completes the command by setting DSTS.RSS to '0'. Reset Source: rst_mod_g_rst_n |
| 24 | SSS | R | 0h | SSS Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process, it completes the command by setting DSTS.SSS to '0'. Reset Source: rst_mod_g_rst_n |
| 23 | COREIDLE | R | 0h | Core Idle The bit indicates that the controller finished transferring all RxFIFO data to system memory, Writing out all completed descriptors, and all Event Counts are zero. Note: While testing for Reset values, mask out the read value. This bit represents the changing state of the controller and does not hold a static value. Reset Source: rst_mod_g_rst_n |
| 22 | DEVCTRLHLT | R | 1h | Device Controller Halted This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1. The controller sets this bit to 1 when, after SW sets Run/Stop to 0, the controller is idle and the lower layer finishes the disconnect process. When Halted=1, the controller does not generate Device events. Note: - The controller does not set this bit to 1 if GEVNTCOUNTn has some valid value. Software needs to acknowledge the events that are generated [by Writing to GEVNTCOUNTn] while it is waiting for this bit to be set to 1. - When Interrupt Moderation is enabled, there could be delay in raising the interrupt line when the event count is non-zero. Software should read the GEVNTCOUNT register directly and acknowledge them. Reset Source: rst_mod_g_rst_n |
| 21:18 | USBLNKST | R | 4h | USBLNKST. USB/Link State In SS mode: LTSSM State - 4'h0: U0 - 4'h1: U1 - 4'h2: U2 - 4'h3: U3 - 4'h4: SS_DIS - 4'h5: RX_DET - 4'h6: SS_INACT - 4'h7: POLL - 4'h8: RECOV - 4'h9: HRESET - 4'ha: CMPLY - 4'hb: LPBK - 4'hf: Resume/Reset In HS/FS/LS mode: - 4'h0: On state - 4'h2: Sleep [L1] state - 4'h3: Suspend [L2] state - 4'h4: Disconnected state [Default state] - 4'h5: Early Suspend state [valid only when Hibernation is disabled, GCTL[1].GblHibernationEn = 0] - 4'he: Reset [valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1] - 4'hf: Resume [valid only when Hibernation is enabled, GCTL[1].GblHibernationEn = 1] The link state Resume/Reset indicates that the controller received a resume or USB reset request from the host while the link was in hibernation. Software must write '8' [Recovery] to the DCTL.ULStChngReq field to acknowledge the resume/reset request. When Hibernation is enabled, GCTL[1].GblHibernationEn = 1, this field USBLnkSt is valid only when DCTL[31].Run/Stop set to '1' and DSTS[29].DCNRD = 0. The Early Suspend link state is an early indication of device suspend in HS/FS. The link state changes to Early Suspend after detecting bus idle for 3ms. - In HS operation, this is an indication that the USB bus [that is, LineState] has been in idle [SE0] for 3ms. However, it does not confirm whether the next process is Suspend or Reset. The device checks the bus again after pull up enable delay and if the line state indicates Suspend [full speed J], then the device waits for an additional time [~3ms] to indicate the actual Suspend state. - In FS operation, this is an indication that the USB bus [that is, LineState] has been in idle [J] for 3ms. The device waits for an additional time [~3ms of Idle] to indicate the actual Suspend state. Reset Source: rst_mod_g_rst_n |
| 17 | RXFIFOEMPTY | R | 1h | RxFIFO Empty. Reset Source: rst_mod_g_rst_n |
| 16:3 | SOFFN | R | 0h | Frame/Microframe Number of the Received SOF. When the controller is operating at SuperSpeed, - [16:3] indicates the uframe/ITP number When the controller is operating at high-speed, - [16:6] indicates the frame number - [5:3] indicates the microframe number When the controller is operating at full-speed, - [16:14] is not used. Software can ignore these 3 bits - [13:3] indicates the frame number Note: After power-on reset, the controller generates the microframe number internally for every 125us if the USB host has not issued SOF/ITP yet. During P3 state, the duration of SOFFN is based on the suspend_clk frequency. Reset Source: rst_mod_g_rst_n |
| 2:0 | CONNECTSPD | R | 4h | Connected Speed [ConnectSpd]
Indicates the speed at which the DWC_usb3 controller has come up after speed detection through a chirp sequence.
- 3'b100: SuperSpeed [PHY clock is running at 125 or 250 MHz]
- 3'b000: High-speed [PHY clock is running at 30 or 60 MHz]
- 3'b001: Full-speed [PHY clock is running at 30 or 60 MHz]
Low-speed is not supported for devices using a UTMI+ PHY. 0 HighSpeed 1 FullSpeed 4 SuperSpeed |