SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC, regardless of USB traffic conditions. To independently validate configuration settings, software may use the following algorithm to convert the inter-interrupt Interval value to the common 'interrupts/sec' performance metric.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 0464h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| IMODC | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| IMODC | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IMODI | |||||||
| R/W | |||||||
| FA0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMODI | |||||||
| R/W | |||||||
| FA0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | IMODC | R/W | 0h | Interrupt Moderation Counter [IMODC] - RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0', counts down to '0', and stops. The associated interrupt is signaled whenever this counter is '0', the Event Ring is not empty, the IE and IP flags = '1', and EHB = '0'. This counter may be directly written by software at any time to alter the interrupt rate. Reset Source: rst_mod_g_rst_n |
| 15:0 | IMODI | R/W | FA0h | Interrupt Moderation Interval [IMODI] - RW. Default = '4000' [~1ms]. Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of '0' disables interrupt throttling logic and interrupts is generated immediately if IP = '0', EHB = '0', and the Event Ring is not empty. Reset Source: rst_mod_g_rst_n |