SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
USB Status Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 0024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_13 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_13 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_31_13 | HCE | CNR | SRE | RSS | SSS | ||
| R | R | R | R/W1TC | R | R | ||
| 0h | 0h | 1h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_7_5 | PCD | EINT | HSE | RESERVED_1 | HCH | ||
| R | R/W1TC | R/W1TC | R/W1TC | R | R | ||
| 0h | 0h | 0h | 0h | 0h | 1h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED_31_13 | R | 0h | Reserved |
| 12 | HCE | R | 0h | Host Controller Error [HCE] - RO Default = 0. '0' = No internal xHC error conditions exist and '1' = Internal xHC error condition. This flag must be set to indicate that an internal error condition has been detected which requires software to reset and reinitialize the xHC. Refer to section 4.24.1 of the Databook for more information. Reset Source: rst_mod_g_rst_n |
| 11 | CNR | R | 1h | Controller Not Ready [CNR] - RO Default = '1'. '0' = Ready and '1' = Not Ready. Software must not write to thes Doorbell or Operational register of the xHC, other than the USBSTS register, until CNR = '0'. This flag is set by the xHC after a Chip Hardware Reset and cleared when the xHC is ready to begin accepting register writes. This flag remains cleared ['0'] until the next Chip Hardware Reset. Reset Source: rst_mod_g_rst_n |
| 10 | SRE | R/W1TC | 0h | Save/Restore Error This bit is currently not supported. Reset Source: rst_mod_g_rst_n |
| 9 | RSS | R | 0h | Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller has finished the restore process, it completes the command by setting DSTS.RSS to '0'. Reset Source: rst_mod_g_rst_n |
| 8 | SSS | R | 0h | Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process, it completes the command by setting DSTS.SSS to '0'. Reset Source: rst_mod_g_rst_n |
| 7:5 | RESERVED_7_5 | R | 0h | Reserved |
| 4 | PCD | R/W1TC | 0h | Reset Value for PCD Reset Source: rst_mod_g_rst_n |
| 3 | EINT | R/W1TC | 0h | Reset Value for EINT Reset Source: rst_mod_g_rst_n |
| 2 | HSE | R/W1TC | 0h | HSE For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0.. Reset Source: rst_mod_g_rst_n |
| 1 | RESERVED_1 | R | 0h | Reserved |
| 0 | HCH | R | 1h | HCH For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |