SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Structural Parameters 1 Register For register definitions, refer to the xHCI specification.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MAXPORTS | |||||||
| R | |||||||
| 1h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_23_19 | MAXINTRS | ||||||
| R | R | ||||||
| 0h | 8h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MAXINTRS | |||||||
| R | |||||||
| 8h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAXSLOTS | |||||||
| R | |||||||
| 40h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | MAXPORTS | R | 1h | Number of Ports [MaxPorts] - Number of ports implemented is defined by the parameter [DWC_USB3_HOST_NUM_U2_ROOT_PORTS + DWC_USB3_HOST_NUM_U3_ROOT_PORTS] - Number of ports enabled is controlled by the controller input signals host_num_u2_port[3:0]+host_num_u3_port[3:0] Note: In USB 2.0-only mode, the host_num_u3_port signal is zero. Reset Source: rst_mod_g_rst_n |
| 23:19 | RESERVED_23_19 | R | 0h | Reserved |
| 18:8 | MAXINTRS | R | 8h | Number of Interrupters [MaxIntrs] Defined by the configurable parameter DWC_USB3_HOST_NUM_INTERRUPTER_SUPT Reset Source: rst_mod_g_rst_n |
| 7:0 | MAXSLOTS | R | 40h | Number of device slots [MaxSlots] Defined by configurable parameter DWC_USB3_NUM_DEVICE_SUPT Reset Source: rst_mod_g_rst_n |