SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Enable Clear Register 0
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| USB0 | 0F98 00C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MEM_CTRL_RAM0_ENABLE_CLR | RAMECC_ENABLE_CLR | |||||
| NONE | R/W1TC | R/W1TC | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | NONE | 0h | Reserved |
| 1 | MEM_CTRL_RAM0_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for mem_ctrl_ram0_pend |
| 0 | RAMECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for ramecc_pend |