SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The IRQ_STATUS_RAW_MISC register allows the usbss interrupt sources to be manually set when writing a 1 to a specific bit. Write 0: No action Write 1: Set event Read 0: No event pending Read 1: Event pending
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 0430h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED31_23 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED31_23 | VBUSVALID_CHANGE | RESERVED21 | SESSVALID_CHANGE | RESERVED19_0 | |||
| R | R/W1TS | R | R/W1TS | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED19_0 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED19_0 | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:23 | RESERVED31_23 | R | 0h | Reserved bits |
| 22 | VBUSVALID_CHANGE | R/W1TS | 0h | Set when VBUSVALID changes state Reset Source: cfg_srst_n |
| 21 | RESERVED21 | R | 0h | Reserved bits |
| 20 | SESSVALID_CHANGE | R/W1TS | 0h | Set when SESSVALID changes state Reset Source: cfg_srst_n |
| 19:0 | RESERVED19_0 | R | 0h | Reserved bits |