SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
TRB3 Word 1.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0070 3034h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TRBSTS | RSVD2 | SPR | PCM1 | ||||
| R/W | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | BUFSIZ | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BUFSIZ | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUFSIZ | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | TRBSTS | R/W | 0h | Packet Count M1 Reset Source: cfg_srst_n |
| 27 | RSVD2 | R/W | 0h | Reserved bits Reset Source: cfg_srst_n |
| 26 | SPR | R/W | 0h | Short packet received/Reserved bits Reset Source: cfg_srst_n |
| 25:24 | PCM1 | R/W | 0h | Packet Count M1 Reset Source: cfg_srst_n |
| 23 | RESERVED | NONE | 0h | Reserved |
| 22:0 | BUFSIZ | R/W | 0h | Buffer Size Reset Source: cfg_srst_n |