SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
TRB0 Word 0.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0070 3000h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD2 | SID | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SID | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SID | RSVD1 | IOC | ISP_IMI | TRBCTL | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRBCTL | CSP | CHN | LST | HWO | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RSVD2 | R/W | 0h | Reserved bits Reset Source: cfg_srst_n |
| 29:14 | SID | R/W | 0h | Stream ID / SOF Number Reset Source: cfg_srst_n |
| 13:12 | RSVD1 | R/W | 0h | Reserved bits Reset Source: cfg_srst_n |
| 11 | IOC | R/W | 0h | Interrupt on Complete Reset Source: cfg_srst_n |
| 10 | ISP_IMI | R/W | 0h | Interrupt on Short Packet / Interrupt on Missed ISOC Reset Source: cfg_srst_n |
| 9:4 | TRBCTL | R/W | 0h | Indicates the type of TRB Reset Source: cfg_srst_n |
| 3 | CSP | R/W | 0h | Continue on Short Packet Reset Source: cfg_srst_n |
| 2 | CHN | R/W | 0h | Chain buffers Reset Source: cfg_srst_n |
| 1 | LST | R/W | 0h | Indicates this is the last TRB in a list Reset Source: cfg_srst_n |
| 0 | HWO | R/W | 0h | Hardware Owner of Descriptor Reset Source: cfg_srst_n |