SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface. That is to say when the feature is enabled, the clock will be gated off until an OCP command for this device has been detected. When the software reset bit is set high it causes a full device reset.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0054h |
| UART1 | 0281 0054h |
| UART2 | 0282 0054h |
| UART3 | 0283 0054h |
| UART4 | 0284 0054h |
| UART5 | 0285 0054h |
| UART6 | 0286 0054h |
| WKUP_UART0 | 2B30 0054h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | IDLEMODE | ENAWAKEUP | SOFTRESET | AUTOIDLE | |||
| R | R/W | R/W | W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:5 | RESERVED | R | 0h | |
| 4:3 | IDLEMODE | R/W | 0h | POWER MANAGEMENT REQ/ACK CONTROL
REF: OCP DESIGN GUIDELINES VERSION 1.1 0 Force idle. An idle request is acknowledged
unconditionally
1 No-idle. An idle request is never
acknowledged.
2 Smart idle. Acknowledgement to an idle
request is given based in the internal
activity of the module.
3 reserved |
| 2 | ENAWAKEUP | R/W | 0h | WAKE UP FEATURE CONTROL 0 Wake up is disabled 1 Wake up capability is enabled |
| 1 | SOFTRESET | W | 0h | Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. 0 Normal mode 1 The module is reset |
| 0 | AUTOIDLE | R/W | 0h | Internal OCP clock gating strategy 0 Clock is running
1 Automatic OCP clock gating strategy is
applied, based on the OCP interface
activity |