SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IrDA modes only. Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used, when multiple start flags are required in SIR Mode. If only one start flag is required, this will always be 0xC0. If n start flags are required, then either (n-1) 0xC0 or (n-1) 0xFF flags are sent, followed by a single 0xC0 flag (immediately preceding the first data byte).
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0038h |
| UART1 | 0281 0038h |
| UART2 | 0282 0038h |
| UART3 | 0283 0038h |
| UART4 | 0284 0038h |
| UART5 | 0285 0038h |
| UART6 | 0286 0038h |
| WKUP_UART0 | 2B30 0038h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STS_FIFO_RESET | XBOF_TYPE | RESERVED | |||||
| R/W1TS | R/W | R | |||||
| 0h | 1h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7 | STS_FIFO_RESET | R/W1TS | 0h | Status FIFO reset. This bit is self-clearing Reset Source: mod_g_arstn |
| 6 | XBOF_TYPE | R/W | 1h | SIR xBOF select. 0 0xFF 1 0xC0 |
| 5:0 | RESERVED | R | 0h |