SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0004h |
| UART1 | 0281 0004h |
| UART2 | 0282 0004h |
| UART3 | 0283 0004h |
| UART4 | 0284 0004h |
| UART5 | 0285 0004h |
| UART6 | 0286 0004h |
| WKUP_UART0 | 2B30 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EOF_IT | LINE_STS_IT | TX_STATUS_IT | STS_FIFO_TRIG_IT | RX_OVERRUN_IT | LAST_RX_BYTE_IT | THR_IT | RHR_IT |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7 | EOF_IT | R/W | 0h | 0 Disables the received EOF interrupt. 1 Enables the received EOF interrupt. |
| 6 | LINE_STS_IT | R/W | 0h | 0 Disables the receiver line status
interrupt.
1 Enables the receiver line status interrupt. |
| 5 | TX_STATUS_IT | R/W | 0h | 0 Disables the TX status interrupt. 1 Enables the TX status interrupt. |
| 4 | STS_FIFO_TRIG_IT | R/W | 0h | 0 Disables the status FIFO trigger level
interrupt.
1 Enables the status FIFO trigger level
interrupt. |
| 3 | RX_OVERRUN_IT | R/W | 0h | 0 Disables the RX overrun interrupt. 1 Enables the RX overrun interrupt. |
| 2 | LAST_RX_BYTE_IT | R/W | 0h | 0 Disables the last byte of frame in RX FIFO
interrupt.
1 Enables the last byte of frame in RX FIFO
interrupt. |
| 1 | THR_IT | R/W | 0h | 0 Disables the THR interrupt. 1 Enables the THR interrupt. |
| 0 | RHR_IT | R/W | 0h | 0 Disables the RHR interrupt. 1 Enables the RHR interrupt. |