SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The transmit holding register is actually a 64-byte FIFO. The LH writes data to the THR. The data is placed into the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled location zero of the FIFO is used to store the data.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0000h |
| UART1 | 0281 0000h |
| UART2 | 0282 0000h |
| UART3 | 0283 0000h |
| UART4 | 0284 0000h |
| UART5 | 0285 0000h |
| UART6 | 0286 0000h |
| WKUP_UART0 | 2B30 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| THR | |||||||
| W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:0 | THR | W | 0h | TRANSMIT HOLDING REGISTER Reset Source: mod_g_arstn |