SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is actually a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the RHR. If the FIFO is disabled location zero of the FIFO is used to store the single data character. Note: If an overflow occurs the data in the RHR is not overwritten.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0000h |
| UART1 | 0281 0000h |
| UART2 | 0282 0000h |
| UART3 | 0283 0000h |
| UART4 | 0284 0000h |
| UART5 | 0285 0000h |
| UART6 | 0286 0000h |
| WKUP_UART0 | 2B30 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RHR | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:0 | RHR | R | 0h | Receive holding register Reset Source: mod_g_arstn |