SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCSPI0 | 2010 01A0h |
| MCSPI1 | 2011 01A0h |
| MCSPI2 | 2012 01A0h |
| MCSPI3 | 2013 01A0h |
| MCSPI4 | 2014 01A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DAFRDATA | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DAFRDATA | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DAFRDATA | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DAFRDATA | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | DAFRDATA | R | 0h | FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to "1" and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to this register return a null value |