SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register provides transfer levels needed while using FIFO buffer during transfer.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCSPI0 | 2010 017Ch |
| MCSPI1 | 2011 017Ch |
| MCSPI2 | 2012 017Ch |
| MCSPI3 | 2013 017Ch |
| MCSPI4 | 2014 017Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| WCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| WCNT | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| AFL | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AEL | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | WCNT | R/W | 0h | Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started, a read back in this register returns the current SPI word transfer index 0 Counter not used 1 One word FFFE 65534 MCSPI word FFFF 65535 MCSPI word |
| 15:8 | AFL | R/W | 0h | Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes, then the buffer MCSPI_MODULCTRL[AFL] must be set with n-1The size of this register is defined by the generic parameter FFNBYTE 0 1 byte 1 2 bytes FE 255bytes FF 256bytes |
| 7:0 | AEL | R/W | 0h | Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the buffer MCSPI_MODULCTRL[AEL] must be set with n-1 0 1 byte 1 2 bytes FE 255 bytes FF 256bytes |