SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is dedicated to the configuration of the serial port interface.
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| Instance Name | Physical Address |
|---|---|
| MCSPI0 | 2010 0128h |
| MCSPI1 | 2011 0128h |
| MCSPI2 | 2012 0128h |
| MCSPI3 | 2013 0128h |
| MCSPI4 | 2014 0128h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_11 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_11 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_11 | FDAA | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MOA | INITDLY | SYSTEM_TEST | MS | PIN34 | SINGLE | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 1h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED_11 | R | 0h | Reads returns 0 |
| 8 | FDAA | R/W | 0h | FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX[i] and MCSPI_RX[i] registers 0 FIFO data managed by MCSPI_TX(i) and
MCSPI_RX(i) registers.
1 FIFO data managed by MCSPI_DAFTX and
MCSPI_DAFRX registers. |
| 7 | MOA | R/W | 0h | Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 0 Multiple word access disabled 1 Multiple word access enabled with FIFO |
| 6:4 | INITDLY | R/W | 0h | Initial spi delay for first transfer: This register is an option only available in SINGLE controller mode, The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock, No clock output provided to the boundary and chip select is not active in 4 pin mode within this period 0 No delay for first MCSPI transfer. 1 The controller wait 4 MCSPI bus clock 2 The controller wait 8 MCSPI bus clock 3 The controller wait 16 MCSPI bus clock 4 The controller wait 32 MCSPI bus clock |
| 3 | SYSTEM_TEST | R/W | 0h | Enables the system test mode 0 Functional mode 1 System test mode (SYSTEST) |
| 2 | MS | R/W | 1h | Controller/ Target 0 Controller - The module generates the
SPICLK and SPIEN[3:0].
1 Peripheral - The module receives the SPICLK
and SPIEN[3:0]. |
| 1 | PIN34 | R/W | 0h | Pin mode selection: This register is used to configure the SPI pin mode, in controller or target mode If asserted the controller only use SIMO,SOMI and SPICLK clock pin for spi transfers 0 SPIEN is used as a chip-select.
1 SPIEN is not used. In this mode all related
options to chip-select have no meaning. |
| 0 | SINGLE | R/W | 0h | Single channel / Multi Channel [controller mode only] 0 More than one channel will be used in
controller mode.
1 Only one channel will be used in controller
mode. This bit must be set in Force
SPIEN[i] mode. |